EDN

Design verification and debugging FPGA implementations

Verification takes as much as 70% of an ASIC's development time and resources. With growing ASIC complexity, verification problems are growing exponentially. Given the high cost of ASIC mask sets, the ...
EDN

Is FPGA power design ready for concurrent engineering?

When designers address the power requirements and constraints for an FPGA-based design earlier in the development process, it can yield significant competitive advantage in the final implementation of ...
Electronic Design

Best practices for user-programmable FPGA instrumentation

Field programmable gate arrays (FPGAs) are used extensively in today’s electronic assemblies and test engineers are also choosing to incorporate user-programmable FPGA instrumentation as part of their ...
Business Wire

Avery Design Systems Announces SimAccel FPGA Accelerator

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of the SimAccel FPGA-based accelerator to ...
Business Wire

PRO DESIGN Launches New proFPGA XCVU37P FPGA Module for Prototyping and Verification of High Bandwidth Memory Designs

MUNICH--(BUSINESS WIRE)--PRO DESIGN, leading supplier of FPGA based prototyping systems, today launched its new proFPGA XCVU37P FPGA module for its flexible proFPGA product family. This new FPGA ...
Embedded

CPU plus FPGA design flow for software developers: A new tangible reality

Recently, Brian Bailey organized a round table that resulted in a two-part article called Supporting CPUs Plus FPGAs. The experts discussed the evolving reality of systems design based on FPGAs and ...
Embedded

Tackle team-based FPGA design

You see them at almost every user seminar or industry trade show workshop: the Methodology Managers from XYZ Corporation, who describe the system they use to help the company make sense of the ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...
Elektroniknet

SGET publishes the FPGA module standard oHFM

The Standardisation Group for Embedded Technologies (SGET) heralds a paradigm shift in embedded design: With the publication ...
Nasdaq

Lattice Diamond Software Tool Delivers New Enhancements for FPGA Design, Simulation, and Verification

HILLSBORO, Ore.--(BUSINESS WIRE)-- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular FPGA design ...