But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

The phase locked loop, or PLL, is a real workhorse of circuit design. It is a classic feedback loop where the phase of an oscillator is locked to the phase of a ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...

This article discusses the various control mechanisms for MEMS Coriolis Vibratory Gyroscopes (CVG), and how they can be applied with the commercial off-the-shelf HF2LI Lock-in Amplifier. A MEMS ...